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infineon technologies 1 9.01 hys 72vx3xxgr-8 pc100 registered sdram-modules 3.3 v 168-pin registered sdram modules 256 mb, 512 mb & 1 gb densities the hys 72vx3xxgr-8 family are industry standard 168-pin 8-byte dual in-line memory modules (dimms) which are organized as 32m 72, 64m 72 & 128m 72 high speed memory arrays designed with synchronous drams (sdrams) for ecc applications. all control and address signals are registered on-dimm and the design incorporates a pll circuit for the clock inputs. use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the sdram devices. decoupling capacitors are mounted on the pc board. the dimms use a serial presence detects scheme implemented via a serial e 2 prom using the 2-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168-pin dimms provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint. the pcb layout is based on latest industry pc133/pc100 standard gerber files. besides standard pc100 applications, this module family is intended for applications where registered dimm modules are used in ?buffered mode? at a 67 mhz memory bus speed. 168-pin jedec standard, registered 8 byte dual-in-line sdram modules for server main memory applications using memory frequencies up to 100mhz one bank 32m 72 and 64m 72 organization, two bank 128m 72 organization optimized for ecc applications with very low input capacitances programmed latencies: single + 3.3 v ( 0.3 v) power supply programmable cas latency, burst length, and wrap sequence (sequential & interleave) auto refresh (cbr) and self refresh all inputs and outputs are lvttl compatible serial presence detect with e 2 prom utilizes sdrams in tsopii-54 packages with registers and pll.the two bank module uses stacked tsop54 packages. card size: 133.35 mm 43.18 mm with gold contact pads (jedec mo-161) these registered dimm modules support operation in ?registered? and ?buffered? mode cl t rcd t rp 22 2 performance: -8 unit operation mode registered buffered f ck clock frequency (max.) 100 66 mhz t ck clock cycle time (min.) 10 15 ns t ac clock access time (max.) 6 6 ns
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 2 9.01 note: all part numbers end with a place code (not shown), designating the die revision. consult factory for current revisions. example: hys 72v64300gr-8-c2, indicating rev. c2 dies are used for sdram components. ordering information type compliance code description sdram components hys 72v32301gr-8 pc100-222-622r one bank 256 mb reg. dimm 128 mbit (x4) hyb39s128400ct-7.5 with trp<= 15ns hys 72v64300gr-8 pc100-222-622r one bank 512 mb reg. dimm 256 mbit (x4) hyb39s256400ct-7.5 with trp<= 15ns hys 72v128320gr-8 pc100-222-622r two bank 1 gbyte reg. dimm 256 mbit (x4 stacked) hyb39s256400ct-7.5 with trp<= 15ns
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 3 9.01 *) note : both operation modes are supported by this module family pin definitions and functions a0 - a11, a12 address inputs dqmb0 - dqmb7 data mask ba0, ba1 bank selects cs0 - cs3 chip select dq0 - dq63 data input/output rege *) register enable ? h ? or n.c = registered mode ? l ? = buffered mode cb0 - cb7 check bits (x72 organization only) v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe scl clock for presence detect we read/write input sda serial data out cke0 clock enable n.c. no connection clk0 - clk3 clock input ?? address format density organization memory banks sdrams # of sdrams # of row/bank/ columns bits refreshperiodinterval 256 mb 32m 72 1 32m 4 18 12/2/11 4k 64 ms 15.6 s 512 mb 64m 72 1 64m 4 18 13/2/11 8k 64 ms 7.8 s 1gb 128m 72 2 64m 4 36 13/2/11 8k 64 ms 7.8 s pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 du 86 dq32 128 cke0 3dq1 45cs2 87 dq33 129 cs3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v dd 48 du 90 v dd 132 n.c. 7dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n.c. 92 dq37 134 n.c. 9 dq6 51 n.c. 93 dq38 135 n.c. 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13dq9 55dq16 97dq41 139dq48
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 4 9.01 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n.c. 103 dq46 145 n.c. 20 dq15 62 du 104 dq47 146 du 21 cb0 63 n.c. 105 cb4 147 rege 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n.c. 66 dq22 108 n.c. 150 dq54 25 n.c. 67 dq23 109 n.c. 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 cs1 156 dq59 31 du 73 v dd 115 ras 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 (ap) 80 n.c. 122 ba0 164 n.c. 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 clk1 167 sa2 42 clk0 84 v dd 126 a12 168 v dd pin configuration (cont ? d) pin# symbol pin# symbol pin# symbol pin# symbol
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 5 9.01 block diagram: one bank 32m x 72 & 64m x 72 sdram dimm modules hys72v32301 and hys 72v64300gr using x4 organized sdrams 1) dq wirding may differ from that decribed in this drawing; however dq/dqb relationship must be maintained as shown 2) all resistors are 10 ? unless otherwise noted spb04131 dqm dq0-dq3 d0 dqm dq0-dq3 d1 dqm dq0-dq3 d2 dqm dq0-dq3 d3 dqm dq0-dq3 d16 dq0-dq3 dq4-dq7 rdqmb1 dq8-dq11 dq12-dq15 cb0-cb3 rdqmb0 rcs0 dqm dq0-dq3 d8 dqm dq0-dq3 d9 dqm dq0-dq3 d10 dqm dq0-dq3 d11 dqm dq0-dq3 d17 dq32-dq35 dq36-dq39 rdqmb5 dq40-dq43 dq44-dq47 cb4-cb7 rdqmb4 dqm dq0-dq3 d4 dqm dq0-dq3 d5 dqm dq0-dq3 d6 dqm dq0-dq3 d7 dq16-dq19 dq20-dq23 rdqmb3 dq24-dq27 dq28-dq31 rdqmb2 rcs2 dqm dq0-dq3 d12 dqm dq0-dq3 d13 dqm dq0-dq3 d14 dqm dq0-dq3 d15 dq48-dq51 dq52-dq55 rdqmb7 dq56-dq59 dq60-dq63 rdqmb6 clk0 12 pf pll sdrams d0-d17 clk1, clk2, clk3 12 pf register cs0/cs2 dqmb0-7 ba0, ba1 a0-a11, a12* ) ras cas cke0 we rcs0/rcs2 rdqmb0-7 rba0, rba1 ra0-ra11 rras rcas rcke0 rwe rege 10 k ? sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sdrams d0-d17 sa0 sda sa0 sa1 sa1 sa2 sa2 scl scl wp 47 k ? e 2 prom (256 word x 8 bit) v cc v ss c d0-d17, reg., dll d0-d17, reg., dll v cc * ) a12 is only used for 128 m x 72 organisation cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 6 9.01 block diagram: two bank 128m x 72 sdram dimm modules hys 72v128320gr using stacked x4 organized sdrams spb04132 dqm dq0-dq3 d0 dqm dq0-dq3 d0 dqm dq0-dq3 d1 dqm dq0-dq3 d1 dqm dq0-dq3 d2 dqm dq0-dq3 d2 dqm dq0-dq3 d3 dqm dq0-dq3 d3 dqm dq0-dq3 d16 dqm dq0-dq3 d16 dq0-dq3 dq4-dq7 rdqmb1 dq8-dq11 dq12-dq15 cb0-cb3 rdqmb0 rcs1 rcs0 dqm dq0-dq3 d8 dqm dq0-dq3 d8 dqm dq0-dq3 d9 dqm dq0-dq3 d9 dqm dq0-dq3 d10 dqm dq0-dq3 d10 dqm dq0-dq3 d11 dqm dq0-dq3 d11 dqm dq0-dq3 d17 dqm dq0-dq3 d17 dq32-dq35 dq36-dq39 rdqmb5 dq40-dq43 dq44-dq47 cb4-cb7 rdqmb4 dqm dq0-dq3 d4 dqm dq0-dq3 d4 dqm dq0-dq3 d5 dqm dq0-dq3 d5 dqm dq0-dq3 d6 dqm dq0-dq3 d6 dqm dq0-dq3 d7 dqm dq0-dq3 d7 dq16-dq19 dq20-dq23 rdqmb3 dq24-dq27 dq28-dq31 rdqmb2 rcs3 rcs2 dqm dq0-dq3 d12 dqm dq0-dq3 d12 dqm dq0-dq3 d13 dqm dq0-dq3 d13 dqm dq0-dq3 d14 dqm dq0-dq3 d14 dqm dq0-dq3 d15 dqm dq0-dq3 d15 dq48-dq51 dq52-dq55 rdqmb7 dq56-dq59 dq61-dq63 rdqmb6 clk0 12 pf pll stacked sdrams d0-d17 clk1, clk2, clk3 12 pf register cs0-cs3 dqmb0-7 ba0, ba1 a0-a11, a12* ) ras cas cke0 we rcs0-rcs3 rdqmb0-7 rba0, rba1 ra0-ra11 rras rcas rcke0 rwe rege 10 k ? stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 stacked sdrams d0-d17 * ) a12 is only used for 128 m x 72 organisation sa0 sda sa0 sa1 sa1 sa2 sa2 scl scl wp e 2 prom (256 word x 8 bit) v cc v ss c d0-d17, reg. dll d0-d17, reg. dll 1.) dq wirding may differ from that decribed in this drawing; however dq/dqb relationship must be maintained as shown 2.) all resistors are 10 ? unless otherwise noted v cc 47 k ? cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 7 9.01 absolute maximum ratings dc characteristics t a = 0 to 70 c 1) ; v ss =0v; v dd =3.3v 0.3 v capacitance t a = 0 to 70 c 1) ; v dd =3.3v 0.3 v, f =1mhz parameter symbol limit values unit min. max. input / output voltage relative to v ss v in, v out ? 1.0 4.6 v power supply voltage on v dd to v ss v dd ? 1.0 4.6 v storage temperature range t stg -55 +150 o c power dissipation (per sdram component) p d ? 1w data out current (short circuit) i os ? 50 ma permanent device damage may occur if ? absolute maximum ratings ? are exceeded. functional operation should be restricted to recommended operation conditions. exposure to higher than recommended voltage for extended periods of time affect device reliability parameter symbol limit values unit min. max. input high voltage v ih 2.0 v dd +0.3 v input low voltage v il ? 0.5 0.8 v output high voltage ( i out = ? 4.0 ma) v oh 2.4 ? v output low voltage ( i out =4.0 ma) v ol ? 0.4 v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 10 10 a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) ? 10 10 a parameter symbol limit values unit one bank modules two bank modules input capacitance (all inputs except clk and cke) c in 10 20 pf input capacitance (clk) c clk 30 30 pf input capacitance (cke) c cke 17 30 pf input/output capacitance (dq0 - dq63, cb0 - cb7) c io 10 17 pf input capacitance (scl, sa0 - 2) c sc 88pf input/output capacitance (sda) c sd 88pf
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 8 9.01 operating currents per sdram component t a = 0 to 70 c 1) , v dd =3.3v 0.3 v (recommended operating conditions unless otherwise noted) parameter test condition symbol 128mb 256mb unit note max. max. operating current t rc = t rc(min.) , t ck = t ck(min.) outputs open, burst length = 4, cl = 3. all banks operated in random access, all banks operated in ping- pong manner to maximize gapless data access ? i cc1 150 210 ma 2) precharge stand-by current in power down mode cs = v ih(min.) , cke v il(max.) t ck =min. i cc2p 22ma 2) no operating current t ck = min., cs = v ih(min.) , active state (max. 4 banks) cke v ih(min.) i cc3n 45 45 ma 2) cke v il(max.) i cc3p 10 10 ma 2) burst operating current t ck =min., read command cycling ? i cc4 90 120 ma 2), 3) auto refresh current t ck =min., auto refresh command cycling ? i cc5 210 240 ma 2) self refresh current self refresh mode, cke = 0.2 v ? i cc6 1.5 2.5 ma 2)
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 9 9.01 ac characteristics (sdram device specification) 4), 5) t a = 0 to 70 c 1) ; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note min. max. clock and access times clock cycle time cas latency = 3 cas latency = 2 t ck 10 10 ? ? ns ns 8) clock frequency cas latency = 3 cas latency = 2 f ck ? ? 100 100 mhz mhz 8) access time from clock cas latency = 3 cas latency = 2 t ac ? ? 6 6 ns ns ? clock high pulse width t ch 3 ? ns ? clock low pulse width t cl 3 ? ns ? transition time t t 0.5 10 ns ? setup and hold parameters input setup time t is 2 ? ns ? input hold time t ih 1 ? ns ? power down mode entry time t sb ? 1clk ? power down mode exit setup time t pde 1 ? clk ? mode register set-up time t rsc 2 ? clk ? transition time t t 0.5 10 ns ? common parameters row to column delay time t rcd 20 ? ns ? row precharge time t rp 15 ? ns 8) row active time t ras 50 100k ns ? row cycle time t rc 70 ? ns ? activate (a) to activate (b) command period t rrd 2 ? clk ? cas (a) to cas (b) command period t ccd 1 ? clk ?
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 10 9.01 refresh cycle refresh period (128 mb components) t ref ? 15.6 s ? refresh period (256 mb components) t ref ? 7.8 s ? self refresh exit time t srex 1 ? clk 6) read cycle data out hold time t oh 3 ? ns ? data out to low impedance t lz 0 ? ns 7) data out to high impedance t hz 38ns 7) dqm data out disable latency t dqz ? 2clk ? write cycle data input to precharge (write recovery) t wr 2 ? clk 8) dqm write mask latency t dqw 0 ? clk ? ac characteristics (sdram device specification) (cont ? d) 4), 5) t a = 0 to 70 c 1) ; v ss =0v; v dd =3.3v 0.3 v, t t =1ns parameter symbol limit values unit note min. max.
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 11 9.01 notes 1. the registered dimm modules are designed to operate under system operating conditions between 0-55 deg c ambient, 500 mb/sec sustained bandwidth and 0 lfm airflow. operating at higher ambient temperatures needs sufficient air flow to limit the case temperature of the sdram components do not exceed 85 o c. maximum operation frequency of this module family is 100mhz when operating in ? registered mode ? and 67 mhz when in ? buffered mode ? 2. these parameters depend on the cycle rate. all values are measured at 100mhz operation frequency. input signals are changed once during tck excepts for icc6 and for standby currents when tck = infinity. 3. these parameters are measured with continous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the data-out current is excluded. 4. an initial pause of 100 s is required after power-up. then a precharge all banks command must be given followed by eight auto refresh (cbr) cycles before the mode register set operation can begin. also the on- dimm pll must be given enough clock cycles to stabilize before any operation can be guaranteed. 5. ac timing tests have v il = 0.8 v and v ih = 2.0 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1 v/ns edge rate between 0.8 v and 2.0 v. 6. self refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 7. referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. 8. this module family uses sdram components with a write recovery time twr (sometimes also named tdpl) of two clocks and a trp ( ? precharge time ? ) of <=15 ns to achieve proper operation in ? buffered mode ? at a operation frequency of 67 mhz. serial presence detect a serial presence detect storage device - e 2 prom 34c02 - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus) 50 pf i/o measurement conditions for t ac and t oh clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 12 9.01 spd-table for registered dimm modules byte# description spd entry value hex 256 mb 1bank- 512 mb 1bank 1gb 2banks 0 number of spd bytes 128 80 1 total bytes in serial pd 256 08 2 memory type sdram 04 3 number of row addresses (without bs bits) 12/13 0c0d0d 4 number of column addresses 11 0b 0b 0b 5 number of dimm banks 1 01 01 02 6 module data width 72 48 7 module data width (cont ? d) 0 00 8 module interface levels lvttl 01 9 cycle time at cl = 3 10.0 ns a0 10 access time from clock at cl = 3 6.0 ns 60 11 dimm config (error det/corr.) ecc 02 12 refresh rate/type self-refresh, 15.6 / 7.8 s 80 82 82 13 sdram width, primary x4 04 14 error checking sdram data width x4 04 15 minimum t ccd 1clk 01 16 burst length supported 1, 2, 4, 8 0f 17 number of sdram banks 4 04 18 sdram supported cas latencies 2 & 3 06 19 sdram cs latencies 0 01 20 sdram we latencies 0 01 21 sdram dimm module attributes registered/buffered 1f 22 sdram device attributes v dd tol +/ ? 10% 0e 23 min. clock cycle time at cl = 2 10 ns a0 24 max. data access time from clock for cl = 2 6ns 60 25 min. clock cycle time at cl = 1 not supp. 00 26 max. data access time from clock at cl = 1 not supp. 00 27 sdram minimum t rp 15 ns 0f 28 sdram minimum t rrd 20 ns 14 29 sdram minimum t rcd 20 ns 14 30 sdram minimum t ras 50 ns 32 31 module bank density (per bank) 256/ 512 mbyte 40 80 80 32 sdram input setup time 2 ns 20 33 sdram input hold time 1 ns 10
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 13 9.01 34 sdram data input setup time 2 ns 20 35 sdram data input hold time 1 ns 10 36-61 superset information (may be used in future) ? 00 62 spd revision 1.2 12 63 checksum for bytes 0 - 62 ? db 1e 1f 64-125 manufacturer ? s information ? xx 126 frequency specification 100mhz 64 127 details of clocks ? 8f 128+ unused storage locations ? ff spd-table for registered dimm modules (cont ? d) byte# description spd entry value hex 256 mb 1bank- 512 mb 1bank 1gb 2banks
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 14 9.01 package outlines module package jedec mo-161 256 & 512 mbyte registered module based on x4 organised sdrams note: all tolerances are in accordance with the jedec standard 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 0.1 85 94 95 124 125 168 2 17.78 3.125 0.1 4 4 max. 43.18 detail of contacts 2.55 1 +0.5 1.27 1 1.27 66.68 0.25 pll register register l-dim-168-37 register
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 15 9.01 module package jedec mo-161 1 gbyte registered dimm module with stacked x4 sdrams note: all tolerances are in accordance with the jedec standard 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 0.1 85 94 95 124 125 168 2 17.78 3.125 0.1 4 6.8 max. 43.18 detail of contacts 2.55 1 +0.5 1.27 1 1.27 66.68 0.25 pll register l-dim-168-37-s register register
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 16 9.01 functional description these registered dimms achieve high speed data transfer rate up to 100 mhz, when in ? registered mode ? and up to 67 mhz when in ? buffered mode ? . the ? registered mode ? is achieved when the rege input signal is in ? high ? state or the pin is not connected. operation in ? buffered mode ? (rege = ? low ? ) needs careful system design to compensate all input signals for the extra delay time of the register components when in ? buffered mode ? . ? buffered mode ? is limited to 67 mhz operation. registered mode: all control and address signals are synchronized with the positive edge of externally supplied clocks and are registered on-dimm and hence delayed by one clock cycle in arriving at the sdram devices. the use of the on-board register reduces the capacitive loading of the dimm on input control and address signals. the sdram device data lines (dq) are connected directly to the dimm tabs through 10 ohm series resistors. all the following timing diagrams and explanations show dimm operation at the tabs, not sdram operation. the picture below depicts an overview of the effect of the registered mode on the data outputs (dqs) for a read operation. without the registers, the data is delayed according to the device cas latency, in the case two clocks. with the register, the data is delayed according to the device cas latency plus an additional clock cycle. this is known as the dimm cas latency, and in this example is four three. the data path can be thought of as a pipeline in which the register effectively lengthens the pipe by one clock cycle. in case of a burst write command the data-in is delayed one clock due the op-dimm pipeline register also. therefore, data for the first burst write cycle must be applied on the dq pins on the next clock cycle after the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. spt03968 clk read a t0 t1 t2 t3 t4 t5 t6 command dout a0 dout a1 dout a2 dout a3 nop nop nop nop nop cas latency = 2 , dq ? s ck2 t registered dimm burst read operation (bl = 4) device nop dout a1 dout a0 dout a2 dout a3 cas latency = 3 dimm , dq ? s ck3 t one clock added for on-dimm pipeline register reg-dimm latency = 1
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 17 9.01 registered dimm burst write operation (bl = 4) buffered mode: operating margins when registered dimm modules are used in ? buffered mode ? are derived from the post register timing only. for a complete system level timing the system designer must add/ subtract to/from this margin other parameters such as, system to dimm flight time, clow skew, clock jitter, external register clock to output delay etc. the table below shows an example for the post register timing for dimm modules in ? buffered mode ? : tpd.buf.max: the maximum time for the signal to exit the register with rege in a low stgate. this is measured into 0 pf load. tflight.max: the maximum time for the signal to propagate from the register to the sdram property time [ns] set-up property time [ns] hold tpd.buf.max 1.96 tpd.buf.min 0.91 tflight.max 3.43 tflight.min 2.66 tsso.brd.max 0.30 tsso.brd.min 0.0 tsu.sdram 2.00 tholdsdram -1.00 period 15.00 dq ? s the first data element and the write are registered on the next clock edge reg-dimm latency = 1 clk din a0 din a1 extra data is ignored after termination of a burst. don ? t care din a2 din a3 spt03969 t8 nop clk command nop t0 write a t1 nop t2 nop t3 t6 nop t4 nop t5 t7 nop nop
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 18 9.01 tsso.brd.max: the time the flight tine is extended due to simultaneous switching outputs and crosstalk from other signals. tsu.sdram: the set-up required for the sdram inputs. tpd.buf.min . : the minimum time for the signal to exit the register with rege in a low state. this is measured into a 0 pf load. tflight.min: the minimum time for the signal to propagate from the register to the sdram thold.dram: the hold time required for the sdram inputs period: minimum cycle time expressing in ns allowed for operating these registered dimm modules in ? buffered mode ? module label example: hys72v64300gr-8-c2 64mx72 sdram c1w106112256 pc100-222-622r 512mb, sync, 100mhz, cl2,ecc,reg assembled in usa ifx partnumber ifx coding for: - design step - pcb rev. - date code - lot code
hys 72vx3xxgr-8 pc100 registered sdram-modules infineon technologies 19 9.01 rev. changes 13.2.2001 target specification for operation up to 100 mhz in ? registered mode ? and 67 mhz when used in ? buffered mode ? special module family for applications based on intel ? s 460gx chipset, where pc100 modules are used in ? buffered mode ? at 67 mhz maximum ope- ration frequency. uses components with twr = tdpl = 2clock which support trp <= 15ns to gua- rantee operation at 67mhz when these modules are used in ? buffered mode ? 21.6.2001 outline drawings updated and changed to l-dim-168-37 & 37s 29.06.01 absolute maximum rating section added 06.09.2001 scr: thickness of modules with stacked components changed from 6.4 to 6.8 max. datasheet changed from ? preliminary ? to ? final ?

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